1. Field of Invention
Embodiments of the present invention relate generally to methods of fabricating semiconductor devices and, more particularly, to a method of fabricating a nonvolatile memory device with a high dielectric layer being used as an upper insulating layer of a cell gate insulating layer.
2. Description of the Related Art
In general, the memory semiconductor device includes a plurality of cell transistors and functional circuits for operating the plurality of cell transistors. The memory semiconductor devices can be classified into volatile memory devices and nonvolatile memory devices depending on whether or not they can maintain stored information when a power supply is stopped. The volatile memory devices include DRAMs and SRAMs while the nonvolatile memory devices include ROM, EPROM and EEPROM. In keeping with the recent trend toward the portability and miniaturization of the electronic appliances, the demand for these EEPROMs is sharply increasing.
A general type of the EEPROM is a floating gate type flash memory device provided with an electrically insulated conductor, i.e., floating gate. To change the information stored in the cell transistor, the floating gate type flash memory device utilizes the FN tunneling that is a quantum mechanical phenomenon generated owing to a high potential difference. On the functional circuit of the floating gate type flash memory device, a low voltage transistor and a high voltage transistor are disposed together. Generally, the high voltage transistor has a junction region of DDD structure and the low voltage transistor has a junction region of LDD structure. Also, the high voltage transistor has a thicker gate insulating layer, compared with the low voltage transistor. Accordingly, the floating gate type flash memory device three different gate insulating layers for the cell transistor, the high voltage transistor and the low voltage transistor.
However, to simplify the processes, the low voltage transistor and the cell transistor use an oxide simultaneously formed and thus having the same thickness as a gate insulating layer. Therefore, the floating gate type flash memory device uses two different gate insulating layers, i.e., a low voltage gate insulating layer used for both the cell transistor and the low voltage transistor, and a high voltage gate insulating layer used for the high voltage transistor.
Meanwhile, another type of the EEPROM is a trap type flash memory device, which uses an insulating layer as a structure for charge storage instead of the floating gate. The trap type flash memory device includes a cell gate insulating layer comprised of a lower silicon oxide layer, a silicon nitride layer and an upper silicon oxide layer sequentially stacked. The silicon nitride layer that is an insulator is used as the charge storage layer for the trap type flash memory device. Unlike the floating gate type flash memory device, the trap type flash memory device fails to use the low voltage gate insulating layer as the cell gate insulating layer. Accordingly, it is required that the trap type flash memory device be provided with three different thicknesses of gate insulating layer.
In the trap type flash memory device, a method of forming three different thicknesses of gate insulating layer includes forming a high voltage gate insulating layer on a high voltage transistor region. Thereafter, a cell gate insulating layer is formed on an entire surface of a semiconductor substrate including the high voltage gate insulating layer, and is then patterned to form a cell gate insulating layer pattern covering a cell transistor region but exposing a low voltage transistor region and a high voltage transistor region. Thereafter, a low voltage gate insulating layer is formed on an exposed portion of the low voltage transistor region of the semiconductor substrate.
Meanwhile, the patterning of the cell gate insulating layer includes a photolithography and etching process using a photoresist film. At this time, the upper silicon oxide layer has a thin thickness. Therefore, the upper silicon oxide layer is damaged or decreased in thickness during the photolithography process and a subsequent process of removing the photoresist film. Such damage or thinning of the upper silicon oxide layer results in the property deterioration of the trap type semiconductor device.